-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueBreaking High-speed Material Constraints
Do you need specialty materials for your high-speed designs? Maybe not. Improvements in resins mean designers of high-speed boards can sometimes use traditional laminate systems. Learn more in this issue.
Level Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
Opportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
Cadence’s Brad Griffin Digs Deep Into DDR
February 22, 2015 | Kelly Dack, I-Connect007Estimated reading time: 12 minutes
KD: Excellent. Let's talk about serial interfaces. Tell us where they’ve come from and where we’re going with them.
BG: One of the most interesting things in signal integrity is around the serial interfaces and it also sort of mixes with memory interface design as well, which is a parallel bus. With serial interfaces, the way that we typically check compliance on them is by running many signals which we call high-capacity simulation, and by many I mean like millions and tens of millions of bits. We're looking to see how many of those bits actually get transferred correctly. So when you go to the PCI-SIG, the special-interest group, they have a bit-error rate test that they do with hardware. Well we can do the same sort of bit error rate testing with software. Our signal integrity software supports a high-capacity simulation and then lets you look at the eye diagram and just like with PCI-SIG we have that compliance test built into our software.
There are a couple of really interesting things about what's happening in this space. One is the most popular serial interface by far, which is PCI Express. We’ve been at PCIe 3.0 for a few years now, and that’s an 8 Gb/s interface. Most people here at DesignCon are talking about up to 28 or 56 Gb/s, so 8 is a little bit behind the bleeding edge at this point. But what's going to be happening this year is PCI-SIG is going to approve the 4.0 spec, which is moving it to 16. Still maybe not on the bleeding edge, but doubling the data rate is very significant. Here’s one of the cool things we’re showing in our booth: If someone who is using 8 Gb/s today wants to see if their same hardware will support a 16 Gb/s data transfer, we can help them check that feasibility. It’s really quite interesting because you can see by default the answer is probably no, the eye is going to be closed and you’re not going to meet your bit error rate testing. But because these transceivers and receivers have such advanced equalization in them we have what's called algorithmic models that sit on both sides, transmitter and receiver, and this is the same type of stuff we’re going to see in devices that come out and support PCIe 4.0. We can turn on a level of equalization and see if when we boost that signal if we can open up that eye and see if it’s going to meet those compliance requirements that are going to be associated with doubling the date rate from 8 to 16.
That's a pretty interesting thing that's going to be happening in 2015. And when we talked about LPDDR4, that data rate is actually going to go as high as 4266, so that's going to be working in a similar way that serial links were working about two or three years ago. The same equalization that you needed in serial links a few years ago are going to be needed in memory interfaces this year. We will support that with our algorithmic modeling interface. Today we can show AMI modeling associated with DDR4 and LPDDR4 as well as, of course, serial links. It’s just tremendously exciting that, with all this different technology, we get data passed across the ether into the cloud as fast as possible. All this stuff is really exciting, and the fact that we’re able to analyze this and help customers get to market right the first time is what we're really excited about at Cadence, and the Allegro technology is providing that link to getting the product done right the first time.
KD: Thanks for taking the time to talk with me today, Brad.
BG: Thank you, Kelly.
SPONSORED LINKS:
Sigrity™ Portfolio – What’s New
Accurate Power-Aware Simulation for LPDDR4
Enabling Fast and Efficient Product Creation
Cadence® Allegro® Sigrity™ Signal Integrity Integrated High-Speed Design
How a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results
RELATED VIDEO:
Page 3 of 3
Suggested Items
Terran Orbital’s GEOStare SV2 Captures 3 Years of Success in High-Resolution Imaging
05/17/2024 | BUSINESS WIRETerran Orbital Corporation, a global leader in satellite-based solutions primarily serving the aerospace and defense industries, celebrates the 3rd anniversary of its successful GEOStare SV2 mission. Launched on May 15, 2021, from NASA’s Kennedy Space Center in Florida, GEOStare SV2 has surpassed expectations, delivering exceptional results for commercial satellite imagery.
Indium Experts to Present on High-Temperature, Lead-Free Solder Paste and High Reliability Liquid Metal Alloys Poster at ECTC
05/16/2024 | Indium CorporationIndium Corporation Research Associate Kyle Aserian will deliver a presentation at the 74th Electronic Components and Technology Conference (ECTC) on May 31, in Denver, Colorado.
Siemens, Foxconn Team Up to Optimize Forward-thinking Manufacturing
05/16/2024 | FoxconnSiemens AG, a leading technology company, and Hon Hai Technology Group (Foxconn), the world’s largest electronics manufacturer, have signed a memorandum of understanding (MoU) to drive digital transformation and sustainability in smart manufacturing platforms.
TactoTek Licenses IMSE Technology to Polestar for Sustainable Electronics Design Innovation
05/15/2024 | TactoTekPolestar, the Swedish electric performance car brand, and Finnish smart surface pioneer TactoTek, have entered a collaboration to explore integration of Injection Molded Structural Electronics (IMSE) technology into Polestar’s vehicle programs.
SiPearl: Partnership with Samsung Electronics for built-in HBM in Rhea
05/14/2024 | BUSINESS WIRESiPearl, the company building the high-performance low-power European microprocessor for HPC and AI inference, has signed a partnership with Samsung Electronics Co. Ltd., a world leader in advanced memory technology, to equip its Rhea series with Samsung’s advanced memory solution ideal for HPC and AI applications.