Metallization for Semi-Additive Processing of Build-Up Dielectric Materials, Part I: Process Development Overview
June 8, 2010 |Estimated reading time: 9 minutes
IntroductionThe ITRS (International Technology Roadmap for Semiconductors) [1], sponsored by the semiconductor industry associations in Japan, Korea, Europe, Taiwan and the U.S., provides a projection of semiconductor device and package performance capabilities over the next 15 years. The roadmap includes projections of future requirements for increasingly high-speed signal transmission, higher interconnect wiring density and high reliability for future generations of semiconductor packages substrates.While the 2009 ITRS Roadmap chapter for Interconnect (semiconductor packages) has not yet been completed, the 2008 and earlier edition of the roadmap list a series of key performance attributes and performance milestones for semiconductor package substrates, offering a clear indication of the shape of future needs. Requirements listed in the 2008 document may be divided into four categories: Routing density (i.e. via diameters and line/space dimensions), electrical properties (i.e. dielectric constant and loss tangent), mechanical properties (i.e. Tg and coefficients of thermal expansion) and surface finishes.For Flip Chip-Ball Grid Array (FC-BGA) packages, the roadmap projects future requirements for circuit feature dimensions of 8 micron line/space by 2014, with 6 micron line/space needed by 2017.Creation of circuit features in the dimension ranges required in current and projected semiconductor packages can best be achieved by use of semi-additive metallization processes, in which a very thin conductive layer is applied to a dielectric surface, typically by electroless copper metallization. Following creation of a photoresist pattern over this surface, copper electroplating is used to form the circuit features and to form layer to layer connections by filling laser drilled microvias. The final circuit pattern formation requires the photoresist to be removed and the thin metallization to be removed from the areas between the plated features, in a so-called flash etch process. The overall process sequence is shown in Figure 1.Figure 1: Semi-additive metallization process flow (SAP). Continuing demands for higher performance, multi-functionality and size reduction of electronic devices require future generations of semiconductor packages substrates to provide improved high-speed signal transmission capability, higher interconnect wiring density and high system reliability. For manufacturing of package substrates, a Semi-Additive Process (SAP) is widely used with build-up dielectric materials to form the circuit features.Generally, to create adhesion between the dielectric material and the plated deposits, a desmear process is applied to the dielectric material to form surface roughness. The initial conductive metallization layer is then formed by electroless copper plating. Adhesion is obtained at the plated interface by an anchor effect from the surface roughness. However, when the surface roughness profile is reduced, it is not as easy to achieve high adhesion. Since next generation package substrates require the use of a dielectric material with a lower profile surface, in order to meet end-product performance demands, a metallization process giving high adhesion, independent of dielectric material type and degree of surface roughness is indispensable.In this article, we will describe the critical features of metallization processes for such applications.Development BackgroundSAP electroless copper plating processes must meet the four key technical aspects shown in Figure 2. As mentioned previously, minimizing surface roughness of the dielectric material is required to reduce the impact of circuit trace surface roughness on high-speed signal transmission and high adhesion to the low profile surface is necessary to allow fine circuit features to be formed easily. To ensure the highest possible levels of end product reliability, outstanding insulation resistance between circuit traces is required. The coverage properties of the electroless copper plating must be optimized to allow uniform copper deposition at all points within small-diameter blind via holes (achieved by a combination of inhibition of surface plating thickness and enhancement of coverage at the base of via holes). Uniform coverage is also required to allow effective flash etching and also to provide consistent surface conductivity during copper electroplating. High interconnection reliability can be realized through a combination of optimized desmear, catalyzation and electroless copper plating processes. Particular efforts were focused on the following three steps: 1) impact of neutralization on formation of optimum surface roughness during the desmear process, 2) effects of surface conditioning on both adhesion of metallization and insulation resistance and 3) effects of electroless copper plating formulation on metallization adhesion and coverage within the via holes. Figure 2: Key aspects of semi-additive metallization processes. Process Description(1) Permanganate NeutralizationIn general, desmear processes are comprised of three steps: swelling, permanganate and neutralization. Figure 3 illustrates the changes in surface morphology of a very widely used build-up dielectric ABF-GX13 (Ajinomoto Build-up Film, a product of Ajinomoto Fine-Techno Co., Inc.) during the desmear process. The images in Figure 3 show that the surface structure following swelling + permanganate differs greatly from that seen following neutralization. While the resin etching is determined by the swelling and permanganate treatment conditions, the final surface morphology, which will contact the pretreatment and electroless copper process is much more strongly affected by the neutralization process conditions. Using conventional neutralization processes for PTH applications, an uneven surface structure is formed through removal of the entire surface layer. Using optimized neutralization chemistry, the surface roughness (measured using the average roughness Ra) is not greatly altered, but a much more uniformly roughened surface is created. The formation of additional fine anchor points leads to improvements in metallization adhesion and reliability.Figure 3: Surface morphology during dielectric desmear process. Figure 4 shows the performance of the desmear process, using the optimized neutralization chemistry, on 50 μm blind vias formed in ABF-GX13. A uniformly roughened surface was formed and smear was completely removed from the bottoms of via holes. The outstanding copper to copper adhesion was also clearly demonstrated by the tear away of the copper foil inner layer in a via pull test following electrolytic copper plating. Figure 4: Desmear process capability: Blind via cleaning and dielectric adhesion promotion.(2) Conditioning stepAfter desmear, conditioning treatment of the dielectric surface is carried out in order to increase the adsorption of Pd/Sn colloidal catalyst species, which are approximately 1 nm in diameter. The conditioner modifies the surface charge through absorption of positively charged species, which attract the negatively charged colloidal catalyst. The amount of Pd/Sn adsorption and the adsorption state are highly dependent on the type of conditioner and the bath formulation. An optimized conditioner formulation was found to improve the micro-uniformity of catalyst adsorption even though the total overall amount of catalyst adsorption was not changed. While the standard conditioner products produced uneven plating and lower adhesion to dielectric surfaces, use of the optimized conditioner greatly improves the uniformity of catalyst absorption and electroless copper deposition.Surface analysis of the dielectric following treatment with the optimized conditioner showed enhanced formation of hydroxyl and carboxyl groups compared to the product following treatment with a standard conditioner. The additional concentrations of functional groups capable of forming hydrogen bonds formed are believed to increase the degree of chemical bonding interactions between the catalyst species and the dielectric surface. Furthermore, such chemical bonds are believed to become stronger following post-baking steps, due to dehydration reactions.Figure 5 shows the adhesion strength on ABF-GX13 for both conditioners, over a range of Ra values, achieved by varying the duration of permanganate treatment. These results demonstrate the improved performance of the recently developed conditioner. While high adhesion strength can be achieved at higher values of Ra, when using the existing conditioner, it was possible to obtain high adhesion strength even at low values Ra when using the optimized conditioner.Figure 5a: Relationship between Permanganate Treatment Time and Surface Roughness (Ra).Figure 5b: Relationship between of ABF-GX13 surface roughness, adhesion and conditioner formulation.(3) Electroless Copper PlatingIn general, electroless copper plating baths using tartrate as the chelating agent are known to have poorer solution stability, due to the weaker binding of the copper in solution. It has been our experience that better performing electroless copper plating formulations can be obtained using EDTA, due to its higher chelate stability constant. However, there is a tendency for deposition from conventional EDTA-based baths to give higher deposition rates at locations where mass transport is higher, since such formulations often have rapid initial plating rates. Figure 6 shows cross sections of 50 μm blind vias in ABF-GX13, following electroless copper plating, comparing a conventional EDTA-based system with an optimized electroless copper formulation. For the conventional electroless copper bath, virtually no deposition was seen at the base of the blind via holes. In contrast, adjustments to the copper concentration and surfactant in the optimized bath led to very substantial improvements in electroless copper coverage. In addition, the modified formulation completely covered the complex surface morphology, leading to improvements in the adhesion of electroless copper plating to the dielectric material. Figure 6: Comparison of electroless copper coverage and throwing power in 50 µm bind vias. Adhesion Strength Following HAST Trials Using Each Development StepFigure 7 shows values of peel strength, following HAST (1300C/85% Relative Humidity) Tests in which electroless copper plating and 20 μm thick electrolytic copper plating were applied to ABF-GX13, with a surface Ra of approximately 600 nm. These tests allowed evaluation of the performance of the optimized neutralization, conditioning and electroless copper plating processes. While the initial adhesion strength of the combination of the standard conditioner and electroless copper plating bath was found to be 0.63 kgf/cm, following 100 hours of HAST it fell to 0.49 kgf/cm. In contrast, the combination of the optimized conditioner and electroless copper plating formulations, provided an initial strength of 0.71 kgf/cm which was maintained at 0.60 kgf/cm or more, even after 100 hours of HAST. Values of 0.6 kgf/cm represent an adhesion strength sufficient to satisfy end-product performance requirements. The robustness of the process was demonstrated not only by the initial adhesion values, but also by the minimal degradation following HAST testing.Figure 7: Peel strength on ABF-GX13 after HAST testing.Insulation Resistance Following Circuit FormationEvaluation of samples prepared using the optimized metallization process was carried out on samples of ABF-GX13 with an Ra of approximately 600 nm, using a comb pattern with Line / Space = 10/10 μm. Test parts were prepared using a pattern plate process sequence and tests were carried out with applied voltage (HAST: 130°C/85% RH, bias voltage: DC 5V). The results showed insulation resistances of 1 x 108 Ω, even after 100 hours of testing, indicating acceptable insulation resistance between circuit features even at 10 micron pitch.SummaryThe results of evaluations of an optimized electroless copper metallization process, designed for SAP processing of build-up dielectric materials, demonstrate the benefits of optimization of neutralization, conditioning, and electroless copper plating processes. High density wiring structures processed in the new process enable higher speed signal transmission, while providing high levels of system reliability. The following features make it highly suitable for processing substrates for the next generation of semiconductor packages. *Low dielectric roughness combined with high copper to dielectric adhesion.*Outstanding electroless copper plating coverage properties in blind via holes.*Outstanding via hole interconnection reliability.*High insulation resistance between circuit features.Application of the processes to next generation build-up dielectric materials will be described in Part 2 of the article.References1. International Technology Roadmap for Semiconductors: www.itrs.net.
Hiroyuki Nishiwaki is R&D Project Leader for Metallization Product Development in the Interconnect Technologies group of Dow Electronic Materials. He may be reached at nishiwakih@dow.com.Katsuhiro Yoshida and Shenghua Li are Research Scientists in the Metallization Product R&D group.Dow Electronic Materials is a global supplier of a comprehensive range of printed circuit fabrication products, including dielectric pretreatment and metallization and a full range of via filling processes for HDI and packaging substrate applications.