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This column originally appeared in the December 2012 issue of The PCB Design Magazine.
Few designers ever venture to the shops that will or might build their boards, even when those manufacturers are practically next door. Even one hour spent watching fabrication processes firsthand could avoid stalling some future project for weeks while the design is re-spun to account for actual manufacturing tolerances.
In this inaugural column, I’ll dwell on the mismatch between design rules and process limits, because the shops that specialize in building complex prototypes encounter these issues day in and day out.
If you anticipate that you’ll never layout boards with more than two layers, or holes, traces and spaces smaller than 10 mils, and you’re sure you’ll never have to deal with impedance control, you have no reason other than curiosity to investigate how your boards are constructed. But if you take your job seriously, especially if you may one day route a circuit involving a BGA with a pin pitch tighter than 0.5 mm or one with 1,000 pins, and certainly if you must control impedance, it is imperative that you grasp the accuracy of the electrochemical, thermal, and mechanical operations at your current or prospective manufacturer, as well as the true stability of materials, to understand how excursions from nominal values within tolerance can accumulate and kill a design. I’m tempted to mention ivory towers, but you get the picture.
Inexperienced designers often misconstrue as ironclad the dimensions manufacturers list on their websites. For example, manufacturers – including my facility – may state that they’re capableof producing traces as fine as 2 mils wide on 2-mil spacing. I don’t doubt most of them can, but only under very limited circumstances, namely, only on an inner layer when plating isn’t involved (and absolutely not in buildup layers with buried vias). The problem isn’t the 2-mil traces: It’s the spacing.
You want 2-mil traces on 10-mil or 3-mil spacing? OK. But don’t expect less than plus or minus 25% variation along a 2-mil space no matter the distance. This obviously rules out controlling the impedance of a differential pair of those dimensions.
You might not lose sleep over tolerances for dielectric thickness, but Z-axis variation within the boundaries of a material spec compounds the challenge manufacturers face to meet impedance requirements in HDI projects, when the dielectric height driving a customer’s architecture doesn’t jibe with the blind-hole size in the design to permit a 1:1 or .75:1 via aspect ratio.
There’s no way to fudge the microvia aspect ratio. So, if a design is based on a 6-mil dielectric, but uses 4-mil vias with 8-mil pads, and the via locations and trace spacing are too tight to enlarge the pads and therefore the vias, the only way the board can be built is by decreasing the dielectric height. However, if impedance must be held to 50 ohms for traces on the top or 100 ohms for differential traces, and the dielectric height needs to be decreased by half to salvage the layout, then the trace widths and spacing must be reduced by half.
Ten percent above or below nominal thickness holds true for dielectrics down to .031” cores, but with a 6-mil core, for example, the tolerance is plus or minus 1 mil. Decreasing the dielectric thickness by half would consequently throw impedance control out the window, and narrowing the trace width and spacing by half most likely would as well. Manufacturers can adjust processes only so far to compensate for imbalanced designs. When you consider transmission line effects, there’s an optimum combination of rules that must be in place to guide the layout. A certain dielectric drives a certain minimum via size, which dictates a certain pad size, which determines trace width and therefore spacing.
Finished trace thickness has a negligible bearing on impedance, but you should know how your choice of copper weight influences manufacturing, which a plant tour can clarify. The copper weight you choose governs how readily fine lines can be etched within tolerance, but there are other implications. The general but not absolute rule to follow on inner layers, except HDI layers, is to use half-ounce copper.
But if you have an inner layer with vias that will be stacked, for example, after the vias are plated they will have to be filled, planarized, and then wrap plated. Any via that must be filled must be wrap plated. If you start with half-ounce copper, the trace thickness will exceed 1 mil after those operations, which may be too tall for a single thickness of dielectric in prepreg to conform and fill around features. To avoid that manufacturing issue, you should specify quarter-ounce copper weight as the starting point for such a layer. You would learn during a plant tour that finished thickness after plating is what counts the most, and that is what should limit copper weight, preprocessing.
Have I convinced you to take a field trip yet? Your prototype builder or prospective builder should be happy to arrange a tour, but what questions should you ask? If you have a design in progress, preview it so hole sizes, pad sizes, dielectrics and the like can be discussed up front, especially if it’s a controlled-impedance design or you’re planning to use microvias or sequential laminations.
The processes you’ll see in person will undoubtedly look different than what you had imagined and will drive home just how abstract are the images on your EDA display. When you’re working with representations 500x the scale of the real thing, you can become cavalier about 1 mil.
While you’re walking, ask your guide to show you jobs in progress based on technology you’ll need. For example, if you have a design in the works (or plan to) with 5-mil traces and spaces, sequential laminations, and laser vias, ask to see something of that sort being built. If your host has to duck into the sales manager’s office to find a sample, chances are the technology is not routine for the shop. There should be plenty of examples along the route.
If you don’t contemplate turning to an HDI architecture, why bother looking for laser drills and laser direct imagers at the shop? But if you do, those machines should be in place and busy on site, if the company does many such jobs.
Look for processes that are self-auditing; in other words, they are not dependent upon a person flagging an out-of-range condition. There is no substitute for experience, but no operator is 100% vigilant. If you see 30 or 40 processes being automatically monitored in real time with the status displayed on screens, chances are you’ve found a dependable shop. If instead you see paper check sheets on clipboards, you might have second thoughts.
Perhaps you had quality issues from another supplier but know the root cause of the problem. Naturally you’d enquire about measures the prospective shop takes to prevent this. For example, if your boards had small holes with a high aspect ratio and there were plating issues, you’d be interested to know whether the electroless copper line has vibration to work loose bubbles trapped in small holes, and whether boards similar to yours make two passes for security. And you would check to make sure the plating line has pulse plating to ensure plating extends the length of the holes.
I’m not talking about the kind of detailed investigation that takes place over several days during a customer audit to validate a supplier for production runs after successful prototypes. I’m talking about getting educated about what really happens after your design files reach a fabricator, about understanding the important variables in manufacturing and the limits of processes.
You’ll learn about the interdependencies among processes, how everything works together, how excursions within tolerance from process to process can stack up and defeat your design, and how to tailor design rules to avoid manufacturing issues. You’ll be a better designer for it and a more valuable asset to your company.
Amit Bahl directs sales and marketing at Sierra Circuits, a PCB manufacturer in Sunnyvale, California. He can be reached via email@example.com.