The ability to simulate complex PCB design has become a critical factor in the success of a project. Today’s high-speed processors and SERDES interfaces coupled with sometimes unrealistic time-to-market requirements are pushing design teams toward more nimble development processes. However, there is no point in completing a design on time if it does not work!
To ensure the prototype has first-pass success, designers need to perform accurate board-level simulation, throughout the entire design process. But the challenge is how do you quickly perform the simulation if all the models for the board are not available and if the simulation setup time is prohibitive? Enter the I/O Buffer Information Specification (IBIS). This specification is a fast and accurate behavioral method of modeling input/output buffers based on I-V curve data derived from measurements or full circuit simulation.
Figure 1 depicts the Ibis (bird). With its greedy, little black eyes and its long, trash-probing beak, the Ibis has readily adapted to its environment. We Australians colloquially call it “the bin chicken” since its six-inch curved beak has been sculptured by evolution to effortlessly reach to the bottom of a Macca’s (McDonald’s) fries container.
Getting back to simulation, before the release of the IBIS specification, SPICE transistor-level models were the only consistent method by which circuit models could be created. However, transistor-level models are not well suited to simulate an entire multilayer PCB containing several hundred nets and drivers. Also, semiconductor vendors that generate the models for their integrated circuits do not readily give these models out since they can disclose proprietary information that is confidential, including circuit nodal connections and underlying fabrication processes parameters. Meanwhile, the IBIS model does not require proprietary information about the modeled circuit since no process or circuit design information is disclosed.
The IBIS models are accurate since nonlinear aspects of I/O structures as well as package parasitics, on-die termination (ODT), and ESD structures are considered in the model parameters. More recently, power-aware models have been specified to combine signal integrity (SI) and power integrity (PI) simulation. Since the IBIS is behavioral, the simulation time for a model can run some 25 times faster than a structural model such as that used in SPICE. In addition, IBIS does not have non-convergence issues encountered in SPICE models that prevent the simulator from reaching a valid solution within a certain number of iterations. Now, most EDA vendors support the IBIS specification as the defacto simulation standard.
To read this entire column, which appeared in the April 2019 issue of Design007 Magazine, click here.